A primary consideration in the economical manufacture of metal oxide semiconductor (MOS) large scale integrated (LSI) circuits is minimizing the amount of substrate material, such as silicon, required to produce the integrated circuit chips, thus allowing a greater chip yield per substrate wafer. The surface geometry of the MOS devices formed on the chips and the interconnection pattern of conductors therebetween must be optimized to provide the highest functional component density in order to reduce overall chip area per circuit function. Minimum geometry spacings between metalization lines, diffused regions and polycrystalline silicon conductors must be maintained, yet the length of such lines and their associated capacitance must be minimized in order to optimize circuit performance as the complex interconnection patterns are implemented. Parasitic electrical effects on the circuitry also must be minimized or compensated for in the chip layout. A very high degree of creativeness is thus required of the chip architect in order to choose a particular layout and interconnection pattern for an LSI circuit from the very large number of possibilities that exist for arranging such a circuit. Frequently, the commercial success for a MOS LSI product may hinge on the ability of the chip architect to achieve an optimum chip topography.
The present invention is a MOS LSI Data Encryption Standard (DES) chip having an optimum chip topography and designed to encrypt and decrypt 64-bit blocks of data using the algorithm specified in Federal Information Processing Standards Publication No. 46. The MOS DES chip is designed to be incorporated in electronic communications circuitry, for use in such applications as secure brokerage transactions, electronic funds transfers, secure banking and business accounting computer mainframe communications, remote and host computer communications, secure data storage, and secure packet switching transmissions. By creatively structuring the topographic layout of the DES circuitry, the present invention allows a MOS chip size of 197 mils by 219 mils, with a processing speed of approximately 1.95 megabits per second. The DES circuit in operation encrypts a 64-bit clear text word using a 56-bit user-specified keyword to produce a 64-bit cipher text word. When the present invention is reversed under user control, a 64-bit cipher text word is decrypted to produce the original 64-bit clear text word. The preferred embodiment of the present invention is fabricated in N-channel, self-aligned silicon gate MOS technology and is compatible on all inputs and outputs with transistor-transistor logic.